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preliminary 8/18/97 publication# 20375 rev: c amendment/ +1 issue date: august 1997 am29f800t/am29f800b 8 megabit (1,048,576 x 8-bit/524,288 x 16-bit) cmos 5.0 volt-only, sector erase flash memory distinctive characteristics n 5.0 v 10% for read and write operations minimizes system level power requirements n compatible with jedec standards pinout and software compatible with single-power-supply flash superior inadvertent write protection n package options 44-pin so 48-pin tsop n minimum 100,000 write/erase cycles guaranteed n high performance 70 ns maximum access time n sector erase architecture one 16 kbyte, two 8 kbytes, one 32 kbyte, and fifteen 64 kbytes any combination of sectors can be erased. also supports full chip erase. n sector protection hardware method that disables any combination of sectors from write or erase operations. implemented using standard prom programming equipment. n embedded erase algorithm automatically pre-programs and erases the chip or any sector n embedded program algorithm automatically programs and verifies data at specified address n data polling and toggle bit feature for detection of program or erase cycle completion n ready/busy output (ry/by ) hardware method for detection of program or erase cycle completion n erase suspend/resume supports reading data from or programming data to a sector not being erased n low power consumption 20 ma typical active read current for byte mode 28 ma typical active read current for word mode 30 ma typical program/erase current n enhanced power management for standby mode 1 m a typical standby current n boot code sector architecture t = top sector b = bottom sector n hardware reset pin resets internal state machine to the read mode general description the am29f800 is an 8 mbit, 5.0 volt-only flash mem- ory organized as 1 mbyte of 8 bits each or 512k words of 16 bits each. for flexible erase capability, the 8 mbits of data are divided into 19 sectors as follows: one 16 kbyte, two 8 kbyte, one 32 kbyte, and fifteen 64 kbyte. eight bits of data appear on dq0Cdq7 in byte mode; in word mode 16 bits appear on dq0Cdq15. the am29f800 is offered in 44-pin so and 48-pin tsop packages. this device is designed to be programmed in-system with the standard system 5.0 volt v cc sup- ply. a v pp of 12.0 volts is not required for program or erase operations. the device can also be programmed in standard eprom programmers. the standard am29f800 offers access times of 70 ns, 90 ns, 120 ns, and 150 ns, allowing high-speed micropro- cessors to operate without wait states. to eliminate bus contention, the device has separate chip enable (ce ), write enable (we ), and output enable (oe ) controls. the am29f800 is entirely command set compatible with the jedec single-power-supply flash standard. commands are written to the command register using standard microprocessor write timings. register con- tents serve as input to an internal state-machine which controls the erase and program circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out
2 am29f800t/am29f800b 8/18/97 preliminary of the device is similar to reading from 12.0 volt flash or eprom devices. the am29f800 is programmed by executing the pro- gram command sequence. this will invoke the embed- ded program algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the device automat- ically times the erase pulse widths and verifies proper cell margin. this device also features a sector erase architecture. this allows for sectors of memory to be erased and re- programmed without affecting the data contents of other sectors. a sector is typically erased and verified within 1.5 seconds. the am29f800 is erased when shipped from the factory. the am29f800 device also features hardware sector protection. this feature will disable both program and erase operations in any combination of nineteen sec- tors of memory. amd has implemented an erase suspend feature that enables the user to put erase on hold for any period of time to read data from or program data to a sector that was not being erased. thus, true background erase can be achieved. the device features single 5.0 volt power supply oper- ation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector au- tomatically inhibits write operations during power tran- sitions. the end of program or erase is detected by the ry/by pin. data polling of dq7, or by the toggle bit (dq6). once the end of a program or erase cycle has been completed, the device automatically resets to the read mode. the am29f800 also has a hardware reset pin. when this pin is driven low, execution of any embed- ded program algorithm or embedded erase algorithm will be terminated. the internal state machine will then be reset into the read mode. the reset pin may be tied to the system reset circuitry. therefore, if a system reset occurs during the embedded program algorithm or embedded erase algorithm, the device will be auto- matically reset to the read mode and will have errone- ous data stored in the address locations being operated on. these locations will need re-writing after the reset. resetting the device will enable the sys- tems microprocessor to read the boot-up firmware from the flash memory. amds flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective- ness. the am29f800 memory electrically erases all bits within a sector simultaneously via fowler-nor- dhiem tunneling. the bytes/words are programmed one byte/word at a time using the eprom program- ming mechanism of hot electron injection.
8/18/97 am29f800t/am29f800b 3 preliminary product selector guide block diagram family part no: am29f800 ordering part no: v cc = 5.0 v 10% -70 -90 -120 -150 max access time (ns) 70 90 120 150 ce (e ) access (ns) 70 90 120 150 oe (g ) access (ns) 30 35 50 55 erase voltage generator input/output buffers data latch y-gating cell matrix x-decoder y-decoder address latch chip enable output enable logic pgm voltage generator timer v cc detector state control command register we ce oe a0Ca18 stb stb dq0Cdq15 ry/by buffer ry/by byte reset aC1 v cc v ss 20375c-1
4 am29f800t/am29f800b 8/18/97 preliminary connection diagrams 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 so 20375c-2 ry/by a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 ce v ss oe dq0 dq8 dq1 dq9 dq2 dq10 dq3 dq11 reset we a8 a9 a10 a11 a12 a13 a14 a15 a16 byte v ss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v cc 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
8/18/97 am29f800t/am29f800b 5 preliminary connection diagrams 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 a16 dq2 byte v ss dq15/a-1 dq7 dq14 dq6 dq13 dq9 dq1 dq8 dq0 oe v ss ce a0 dq5 dq12 dq4 v cc dq11 dq3 dq10 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 a15 a18 a14 a13 a12 a11 a10 a9 a8 nc nc we reset nc nc ry/by a1 a17 a7 a6 a5 a4 a3 a2 standard tsop 20375c-3 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 a15 a18 a14 a13 a12 a11 a10 a9 a8 nc nc we reset nc nc ry/by a1 a17 a7 a6 a5 a4 a3 a2 a16 dq2 byte v ss dq15/a-1 dq7 dq14 dq6 dq13 dq9 dq1 dq8 dq0 oe v ss ce a0 dq5 dq12 dq4 v cc dq11 dq3 dq10 reverse tsop 20375c-4
6 am29f800t/am29f800b 8/18/97 preliminary pin configuration a0Ca18 = 19 addresses byte = selects 8-bit or 16-bit mode ce = chip enable dq0Cdq14 = 15 data inputs/outputs dq15/a-1 = dq15 data input/output, a-1 address mux nc = pin not connected internally oe = output enable reset = hardware reset pin, active low ry/by = ready/busy output v cc = +5.0 volt single-power supply ( 10% for -70, -90, -120, -150) v ss = device ground we = write enable logic symbol 19 16 or 8 dq0Cdq15 a0Ca18 ce (e ) oe (g ) we (w ) a-1 ry/by reset byte 20375c-5
8/18/97 am29f800t/am29f800b 7 preliminary ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of: valid combinations valid combinations list configurations planned to be sup- ported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. temperature range c = commercial (0 c to +70 c) i = industrial (C40 c to +85 c) e = extended (C55 c to +125 c) package type e = 48-pin thin small outline package (tsop) standard pinout (ts 048) f = 48-pin thin small outline package (tsop) reverse pinout (tsr048) s = 44-pin small outline package (so 044) device number/description am29f800 8 megabit (1m x 8-bit/512k x 16-bit) cmos flash memory 5.0 volt-only program and erase am29f800 -70 e c optional processing blank = standard processing b = burn-in b speed option see product selector guide and valid combinations t boot code sector architecture t = top sector b = bottom sector valid combinations AM29F800T-70, am29f800b-70 ec, ei, fc, fi, sc, si am29f800t-90, am29f800b-90 ec, ei, ee, eeb, fc, fi, fe, feb, sc, si, se, seb am29f800t-120, am29f800b-120 am29f800t-150, am29f800b-150
8 am29f800t/am29f800b 8/18/97 preliminary table 1. am29f800 user bus operations (byte = v ih ) table 2. am29f800 user bus operations (byte = v il ) legend: l = logic 0, h = logic 1, x = dont care. see characteristics for voltage levels. notes: 1. manufacturer and device codes may also be accessed via a command register write sequence. refer to table 7. 2. refer to the section on sector protection. read mode the am29f800 has two control functions which must be satisfied in order to obtain data at the outputs. ce is the power control and should be used for device selec- tion. oe is the output control and should be used to gate data to the output pins if a device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time is the delay from the falling edge of oe to valid data at the output pins (assuming the addresses have been stable for at least t acc Ct oe time). standby mode there are two ways to implement the standby mode on the am29f800 device, both using the ce pin. a cmos standby mode is achieved with the ce input held at v cc 0.3v. under this condition the current is typically reduced to less than 5 m a. a ttl standby mode is achieved with the ce pin held at v ih . under this condition the current is typically reduced to 1 ma. operation ce oe we a0 a1 a6 a9 dq0Cdq15 reset autoselect, amd manuf. code (note 1) l l h l l l v id code h autoselect device code (note 1) l l h h l l v id code h read l l x a0a1a6a9 d out h standby hxxxxxxhigh z h output disable l h h x x x x high z h write l h l a0 a1 a6 a9 d in h verify sector protect (note 2) l l h l h l v id code h temporary sector unprotect x xxxxxx x v id hardware reset xxxxxxxhigh z l operation ce oe we a0 a1 a6 a9 dq0Cdq7 dq8Cdq15 reset autoselect, amd manuf. code (note 1) llhlllv id code high z h autoselect device code (note 1) l l h h l l v id code high z h read l l x a0a1a6a9 d out high z h standby hxxxxxxhigh zhigh z h output disable l h h xxxxhigh zhigh z h write l h l a0 a1 a6 a9 d in high z h verify sector protect (note 2) llhlhlv id code high z h temporary sector unprotect xxxxxxx x high zv id hardware reset xxxxxxxhigh zhigh z l
8/18/97 am29f800t/am29f800b 9 preliminary in the standby mode the outputs are in the high imped- ance state, independent of the oe input. output disable with the oe input at a logic high level (v ih ), output from the device is disabled. this will cause the output pins to be in a high impedance state. autoselect the autoselect mode allows the reading of a binary code from the device and will identify its manufacturer and type. this mode is intended for use by program- ming equipment for the purpose of automatically matching the device to be programmed with its corre- sponding programming algorithm. this mode is func- tional over the entire temperature range of the device. to activate this mode, the programming equipment must force v id (11.5 v to 12.5 v) on address pin a9. two identifier bytes may then be sequenced from the device outputs by toggling address a0 from v il to v ih . all addresses are dont cares except a0, a1, and a6 (see table 3). the manufacturer and device codes may also be read via the command register, for instances when the am29f800 is erased or programmed in a system with- out access to high voltage on the a9 pin. the command sequence is illustrated in table 4 (see autoselect com- mand sequence). byte 0 (a0 = v il ) represents the manufacturers code (amd=01h) and byte 1 (a0 = v ih ) the device identifier code (am29f800t = d6h and am29f800b = 58h for x8 mode; am29f800t = 22d6h and am29f800b = 2258h for x16 mode). these two bytes/words are given in the table below. all identifiers for manufacturer and device will exhibit odd parity with dq7 defined as the parity bit. in order to read the proper device codes when executing the autoselect, a1 must be v il (see tables 3 and 4). the autoselect mode also facilitates the determination of sector protection in the system. by performing a read operation at the address location xx02h with the higher order address bits a12Ca18 set to the desired sector address, the device will return 01h for a pro- tected sector and 00h for a non-protected sector. table 3. am29f800 sector protection verify autoselect codes *outputs 01h at protected sector addresses table 4. expanded autoselect code table (b) C byte mode (w) C word mode type a12Ca18 a6 a1 a0 code (hex) manufacturer codeamd x v il v il v il 01h am29f800 device am29f800t byte xv il v il v ih d6h word 22d6h am29f800b byte xv il v il v ih 58h word 2258h sector protection sector address v il v ih v il 01h* type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturer codeamd 01h 0000000000000001 am29f800 device am29f800t(b) (w) d6h 22d6h a-1 0 hi-z 0 hi-z 1 hi-z 0 hi-z 0 hi-z 0 hi-z 1 hi-z 0 1 1 1 1 0 0 1 1 0 0 1 1 1 1 0 0 am29f800b(b) (w) 58h 2258h a-1 0 hi-z 0 hi-z 1 hi-z 0 hi-z 0 hi-z 0 hi-z 1 hi-z 0 0 0 1 1 0 0 1 1 1 1 0 0 0 0 0 0 sector protection 01h 0000000000000001
10 am29f800t/am29f800b 8/18/97 preliminary table 5. sector address tables (am29f800t) note: the address range is a18:a C1 if in byte mode (byte = v il ). the address range is a18:a0 if in word mode (byte = v ih ). a18 a17 a16 a15 a14 a13 a12 sector size (x16) address range (x8) address range sa00000xxx 64 kbytes 32 kwords 00000hC07fffh 00000hC0ffffh sa10001xxx 64 kbytes 32 kwords 08000hC0ffffh 10000hC1ffffh sa20010xxx 64 kbytes 32 kwords 10000hC17fffh 20000hC2ffffh sa30011xxx 64 kbytes 32 kwords 18000hC1ffffh 30000hC3ffffh sa40100xxx 64 kbytes 32 kwords 20000hC27fffh 40000hC4ffffh sa50101xxx 64 kbytes 32 kwords 28000hC2ffffh 50000hC5ffffh sa60110xxx 64 kbytes 32 kwords 30000hC37fffh 60000hC6ffffh sa70111xxx 64 kbytes 32 kwords 38000hC3ffffh 70000hC7ffffh sa81000xxx 64 kbytes 32 kwords 40000hC47fffh 80000hC8ffffh sa91001xxx 64 kbytes 32 kwords 48000hC4ffffh 90000hC9ffffh sa101010xxx 64 kbytes 32 kwords 50000hC57fffh a0000hCaffffh sa111011xxx 64 kbytes 32 kwords 58000hC5ffffh b0000hCbffffh sa121100xxx 64 kbytes 32 kwords 60000hC67fffh c0000hCcffffh sa131101xxx 64 kbytes 32 kwords 68000hC6ffffh d0000hCdffffh sa141110xxx 64 kbytes 32 kwords 70000hC77fffh e0000hCeffffh sa1511110xx 32 kbytes 16 kwords 78000hC7bfffh f0000hCf7fffh sa161111100 8 kbytes 4 kwords 7c000hC7cfffh f8000hCf9fffh sa171111101 8 kbytes 4 kwords 7d000hC7dfffh fa000hCfbfffh sa18111111x 16 kbytes 8 kwords 7e000hC7ffffh fc000hCfffffh
8/18/97 am29f800t/am29f800b 11 preliminary table 6. sector address tables (am29f800b) note: the address range is a18:a C1 if in byte mode (byte = v il ). the address range is a18:a0 if in word mode (byte = v ih ). a18 a17 a16 a15 a14 a13 a12 sector size (x16) address range (x8) address range sa0000000x 16 kbytes 8 kwords 00000hC01fffh 00000hC03fffh sa10000010 8 kbytes 4 kwords 02000hC02fffh 04000hC05fffh sa20000011 8 kbytes 4 kwords 03000hC03fffh 06000hC07fffh sa300001xx 32 kbytes 16 kwords 04000hC07fffh 08000hC0ffffh sa40001xxx 64 kbytes 32 kwords 08000hC0ffffh 10000hC1ffffh sa50010xxx 64 kbytes 32 kwords 10000hC17fffh 20000hC2ffffh sa60011xxx 64 kbytes 32 kwords 18000hC1ffffh 30000hC3ffffh sa70100xxx 64 kbytes 32 kwords 20000hC27fffh 40000hC4ffffh sa80101xxx 64 kbytes 32 kwords 28000hC2ffffh 50000hC5ffffh sa90110xxx 64 kbytes 32 kwords 30000hC37fffh 60000hC6ffffh sa100111xxx 64 kbytes 32 kwords 38000hC3ffffh 70000hC7ffffh sa111000xxx 64 kbytes 32 kwords 40000hC47fffh 80000hC8ffffh sa121001xxx 64 kbytes 32 kwords 48000hC4ffffh 90000hC9ffffh sa131010xxx 64 kbytes 32 kwords 50000hC57fffh a0000hCaffffh sa141011xxx 64 kbytes 32 kwords 58000hC5ffffh b0000hCbffffh sa151100xxx 64 kbytes 32 kwords 60000hC67fffh c0000hCcffffh sa161101xxx 64 kbytes 32 kwords 68000hC6ffffh d0000hCdffffh sa171110xxx 64 kbytes 32 kwords 70000hC77fffh e0000hCeffffh sa181111xxx 64 kbytes 32 kwords 78000hC7ffffh f0000hCfffffh
12 am29f800t/am29f800b 8/18/97 preliminary write device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy any ad- dressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the command register is written to by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever happens later; while data is latched on the rising edge of we or ce , whichever happens first. standard micro- processor write timings are used. refer to ac write characteristics and the erase/pro- gramming waveforms for specific timing parameters. sector protection the am29f800 features hardware sector protection. this feature will disable both program and erase oper- ations in any combination of nineteen sectors of mem- ory. the sector protect feature is enabled using programming equipment at the users site . the device is shipped with all sectors unprotected. alternatively, amd may program and protect sectors in the factory prior to shipping the device (amds expressflash? service). it is possible to determine if a sector is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order address bits a12Ca18 is the desired sector address, will produce a logical 1 at dq0 for a protected sector. see table 3 for autoselect codes. temporary sector unprotect this feature allows temporary unprotection of previ- ously protected sectors of the am29f800 device in order to change data in-system. the sector unprotect mode is activated by setting the reset pin to high volt- age (12v). during this mode, formerly protected sec- tors can be programmed or erased by selecting the sector addresses. once the 12 v is taken away from the reset pin, all the previously protected sectors will be protected again. refer to figures 17 and 18. command definitions device operations are selected by writing specific ad- dress and data sequences into the command register. writing incorrect address and data values or writ- ing them in the improper sequence will reset the device to the read mode. table 7 defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. moreover, both reset/read commands are functionally equivalent, resetting the device to the read mode.
8/18/97 am29f800t/am29f800b 13 preliminary table 7. am29f800 command definitions legend: ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the we or ce pulse. pd = data to be programmed at location pa. data is latched on the rising edge of we or ce pulse. sa = address of the sector to be erased. address bits a18Ca12 uniquely select any sector. notes: 1. all values are in hexadecimal. 2. see tables 1 and 2 for description of bus operations. 3. the data is 00h for an unprotected sector group and 01h for a protected sector group. the complete bus address is composed of the sector address (a18Ca12), a1 = 1, and a0 = 0. 4. read and program functions in non-erasing sectors are allowed in the erase suspend mode. 5. address bits a18Ca11 are dont care for unlock and command cycles. command sequence read/reset (note 2) bus write cycles reqd first bus write cycle second bus read/write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr data addr data addr data addr data addr data addr data reset/read word 1xxx xxf0 ra rd byte f0 autoselect manufacturer id word 3 555 xxaa 2aa xx55 555 xx90 xx00 xx01 byte aaa aa 555 55 aaa 90 00 01 autoselect device id (top boot block) word 3 555 xxaa 2aa xx55 555 xx90 xx01 22d6 byte aaa aa 555 55 aaa 90 02 d6 autoselect device id (bottom boot block) word 3 555 xxaa 2aa xx55 555 xx90 xx01 2258 byte aaa aa 555 55 aaa 90 02 58 autoselect sector protect verify (note 3) word 3 555 xxaa 2aa xx55 555 xx90 (sa) x02 xx00 xx01 byte aaa aa 555 55 aaa 90 (sa) x04 00 01 byte program word 4 555 xxaa 2aa xx55 555 xxa0 pa p d byte aaa aa 555 55 aaa a0 chip erase word 6 555 xxaa 2aa xx55 555 xx80 555 xxaa 2aa xx55 555 xx10 byte aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 sector erase word 6 555 xxaa 2aa xx55 555 xx80 555 xxaa 2aa xx55 sa xx30 byte aaa aa 555 55 aaa 80 aaa aa 555 55 30 erase suspend (note 4) word 1xxx xxb0 byte b0 erase resume word 1xxx xx30 byte 30
14 am29f800t/am29f800b 8/18/97 preliminary read/reset command the read or reset operation is initiated by writing the read/reset command sequence into the command reg- ister. microprocessor read cycles retrieve array data from the memory. the device remains enabled for reads until the command register contents are altered. the device will automatically power-up in the read/ reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value en- sures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read characteristics and waveforms for the specific timing parameters. autoselect command flash memories are intended for use in applications where the local cpu can alter memory contents. as such, manufacture and device codes must be accessi- ble while the device resides in the target system. prom programmers typically access the signature codes by raising a9 to a high voltage. however, multi- plexing high voltage onto the address lines is not gen- erally a desirable system design practice. the device contains an autoselect command operation to supplement traditional prom programming method- ology. the operation is initiated by writing the autose- lect command sequence into the command register. following the command write, a read cycle from ad- dress xx00h retrieves the manufacture code of 01h. a read cycle from address xx01h returns the device code (am29f800t = d6h and am29f800b = 58h for x8 mode; am29f800t = 22d6h and am29f800b = 2258h for x16 mode) (see tables 3 and 4). all manufacturer and device codes will exhibit odd par- ity with dq7 defined as the parity bit. furthermore, the write protect status of sectors can be read in this mode. scanning the sector addresses (a18, a17, a16, a15, a14, a13, and a12) while (a6, a1, a0) = (0, 1, 0) will produce a logical 1 at device output dq0 for a protected sector. to terminate the operation, it is necessary to write the read/reset command sequence into the register. byte/word programming the device is programmed on a byte-by-byte (or word-by-word) basis. programming is a four bus cycle operation. there are two unlock write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever hap- pens first. the rising edge of ce or we (whichever happens first) begins programming using the embed- ded program algorithm. upon executing the algorithm, the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the pro- grammed cell margin. the automatic programming operation is completed when the data on dq7 (also used as data polling) is equivalent to the data written to this bit at which time the device returns to the read mode and addresses are no longer latched (see table 8, hardware sequence flags). therefore, the device requires that a valid ad- dress to the device be supplied by the system at this particular instance of time for data polling operations. data polling must be performed at the memory location which is being programmed. any commands written to the chip during the embed- ded program algorithm will be ignored. if a hardware reset occurs during the programming operation, the data at that particular location will be corrupted. programming is allowed in any sequence and across sector boundaries. beware that a data 0 cannot be programmed back to a 1. attempting to do so may cause the device to exceed programming time limits (dq5 = 1) or result in an apparent success, according to the data polling algorithm, but a read from reset/read mode will show that the data is still 0. only erase op- erations can convert 0s to 1s. figure 1 illustrates the embedded programming algo- rithm using typical command strings and bus operations. chip erase chip erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase. the erase is performed sequentially on all sectors at the same time (see table erase and programming perfor- mance). the system is not required to provide any controls or timings during these operations. the automatic erase begins on the rising edge of the last we pulse in the command sequence and termi- nates when the data on dq7 is 1 (see write opera- tion status section) at which time the device returns to read the mode. figure 2 illustrates the embedded erase algorithm using typical command strings and bus operations.
8/18/97 am29f800t/am29f800b 15 preliminary sector erase sector erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the sector erase command. the sec- tor address (any address location within the desired sector) is latched on the falling edge of we , while the command (30h) is latched on the rising edge of we . after a time-out of 80 m s from the rising edge of the last sector erase command, the sector erase operation will begin. multiple sectors may be erased sequentially by writing the six bus cycle operations as described above. this sequence is followed with writes of the sector erase command to addresses in other sectors desired to be sequentially erased. the time between writes must be less than 80 m s otherwise that command will not be ac- cepted and erasure will start. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-en- abled after the last sector erase command is written. a time-out of 80 m s from the rising edge of the last we will initiate the execution of the sector erase command(s). if another falling edge of the we occurs within the 80 m s time-out window the timer is reset. (monitor dq3 to determine if the sector erase timer window is still open. see dq3, sector erase timer.) any command other than sector erase or erase suspend during this period will reset the device to the read mode, ignoring the pre- vious command string. in that case, restart the erase on those sectors and allow them to complete. loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to18). refer to dq3, sector erase timer, in the write opera- tion status section. sector erase does not require the user to program the device prior to erase. the device automatically pro- grams all memory locations in the sector(s) to be erased prior to electrical erase. when erasing a sector or sectors the remaining unselected sectors are not af- fected. the system is not required to provide any con- trols or timings during these operations. the automatic sector erase begins after the 80 m s time out from the rising edge of the we pulse for the last sector erase command pulse and terminates when the data on dq7, data polling, is 1 (see write operation status section) at which time the device returns to the read mode. data polling must be performed at an ad- dress within any of the sectors being erased. figure 2 illustrates the embedded erase algorithm using typical command strings and bus operations. erase suspend the erase suspend command allows the user to inter- rupt a sector erase operation and then perform data reads or programs to a sector not being erased. this command is applicable only during the sector erase operation which includes the time-out period for sector erase. the erase suspend command will be ignored if written during the chip erase operation or embedded program algorithm. writing the erase suspend com- mand during the sector erase time-out results in imme- diate termination of the time-out period and suspension of the erase operation. any other command written during the erase suspend mode will be ignored except the erase resume command. writing the erase resume com- mand resumes the erase operation. the addresses are dont-cares when writing the erase suspend or erase resume command. when the erase suspend command is written during a sector erase operation, the chip will take a maximum of 20 m s to suspend the operation and go into erase suspended mode, at which time the user can read or program from a sector that is not being erased. read- ing data in this mode is the same as reading from the standard read mode, except that the data must be read from sectors that have not been erase suspended. successively reading from the erase-suspended sec- tor while the device is in the erase-suspend-read mode will cause dq2 to toggle. after entering the erase-sus- pend mode, the user can program the device by writing the appropriate command sequence for byte program. this program mode is known as the erase sus- pend-program mode. again, programming in this mode is the same as programming in regular byte program mode, except that the data must be programmed to sectors that are not erase suspended. successively reading from the erase suspended sector while the de- vice is in the erase suspend-program mode will cause dq2 to toggle. the end of the erase suspend-program operation is detected by the ry/by output pin, data polling of dq7, or by the toggle bit (dq6), which is the same as the regular byte program operation. note that dq7 must be read from the byte program address while dq6 can be read from any address. when the erase operation has been suspended, the de- vice defaults to the erase-suspend-read mode. reading data in this mode is the same as reading from the stan- dard read mode except that the data must be read from sectors that have not been erase-suspended. to resume the operation of sector erase, the resume command (30h) should be written. any further writes of the resume command at this point will be ignored. an- other erase suspend command can be written after the chip has resumed erasing.
16 am29f800t/am29f800b 8/18/97 preliminary write operation status table 8. hardware sequence flags notes: 1. dq2 can be toggled when sector address applied is that of an erasing sector. conversely, dq2 cannot be toggled when the sector address applied is that of a non-erasing sector. dq2 is therefore used to determine which sectors are erasing and which are not. 2. these status flags apply when outputs are read from the address of a non-erase-suspended sector. 3. if dq5 is high (exceeded timing limits), successive reads from a problem sector will cause dq2 to toggle. dq7: data polling the am29f800 device features data polling as a method to indicate to the host that the embedded algo- rithms are in progress or completed. during the em- bedded program algorithm, an attempt to read the device will produce the complement of the data last written to dq7. upon completion of the embedded pro- gram algorithm, an attempt to read the device will pro- duce the true data last written to dq7. during the embedded erase algorithm, an attempt to read the de- vice will produce a 0 at the dq7 output. upon completion of the embedded erase algorithm an attempt to read the device will produce a 1 at the dq7 output. the flowchart for data polling (dq7) is shown in figure 3. for chip erase, the data polling is valid after the rising edge of the sixth we pulse in the six write pulse se- quence. for sector erase, the data polling is valid after the last rising edge of the sector erase we pulse. data polling must be performed at sector addresses within any of the sectors being erased and not a protected sector. otherwise, the status may not be valid. just prior to the completion of embedded algorithm op- erations dq7 may change asynchronously while the output enable (oe ) is asserted low. this means that the device is driving status information on dq7 at one instant of time and then that bytes valid data at the next instant of time. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the embedded algorithm operations and dq7 has a valid data, the data outputs on dq0Cdq6 may be still invalid. the valid data on dq0Cdq7 will be read on the successive read attempts. the data polling feature is only active during the em- bedded programming algorithm, embedded erase al- gorithm, or sector erase time-out (see table 7). see figure 11 for the data polling timing specifications and diagrams. dq6: toggle bit the am29f800 also features the toggle bit as a method to indicate to the host system that the embed- ded algorithms are in progress or completed. during an embedded program or erase algorithm cy- cle, successive attempts to read (oe toggling) data from the device at any address will result in dq6 tog- gling between one and zero. once the embedded pro- gram or erase algorithm cycle is completed, dq6 will stop toggling and valid data will be read on the next successive attempt. during programming, the toggle bit is valid after the rising edge of the fourth we pulse in the four write pulse sequence. for chip erase, the toggle bit is valid after the rising edge of the sixth we pulse in the six write pulse sequence. for sector erase, the toggle bit is valid after the last rising edge of the sector erase we pulse. the toggle bit is active during the sector erase time-out. either ce or oe toggling will cause dq6 to toggle. in addition, an erase suspend/resume command will status dq7 dq6 dq5 dq3 dq2 rdy/bsy in progress byte programming dq7 toggle 0 0 no tog 0 program/erase in auto-erase 0 toggle 0 1 (note 1) 0 erase suspend mode erase sector address 1 no tog 0 1 toggle 1 non-erase sector address data data data data data 1 program in erase suspend dq7 (note 2) toggle 0 1 1 (note 1) 0 exceeded time limits byte programming dq7 toggle 1 0 no tog 0 program/erase in auto-erase 0 toggle 1 1 (note 3) 0 program in erase suspend dq7 toggle 1 1 (note 3) 0
8/18/97 am29f800t/am29f800b 17 preliminary cause dq6 to toggle. see figure 12 for the toggle bit timing specifications and diagrams. dq5: exceeded timing limits dq5 will indicate if the program or erase time has ex- ceeded the specified limits (internal pulse count). under these conditions dq5 will produce a 1. this is a failure condition which indicates that the program or erase cycle was not successfully completed. data poll- ing is the only operating function of the device under this condition. the ce circuit will partially power down the device under these conditions (to approximately 2 ma). the oe and we pins will control the output dis- able functions as described in table 1. the dq5 failure condition will also appear if a user tries to program a 1 to a location that is previously pro- grammed to 0. in this case the device locks out and never completes the embedded program algorithm. hence, the system never reads a valid data on dq7 bit and dq6 never stops toggling. once the device has ex- ceeded timing limits, the dq5 bit will indicate a 1. please note that this is not a device failure condition since the device was incorrectly used. if this occurs, reset the device. dq3: sector erase timer after the completion of the initial sector erase com- mand sequence the sector erase time-out will begin. dq3 will remain low until the time-out is complete. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit indicates the device has been written with a valid erase command, dq3 may be used to determine if the sector erase timer window is still open. if dq3 is high (1) the internally controlled erase cycle has begun; attempts to write subsequent commands (other than erase suspend) to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit. if dq3 is low (0), the device will accept additional sector erase commands. to insure the command has been ac- cepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 were high on the second sta- tus check, the command may not have been accepted. refer to table 8, hardware sequence flags. dq2: toggle bit 2 this toggle bit, along with dq6, can be used to deter- mine whether the device is in the embedded erase algorithm or in erase suspend. successive reads from the erasing sector will cause dq2 to toggle during the embedded erase algorithm. if the device is in the erase suspend-read mode, suc- cessive reads from the erase-suspend sector will cause dq2 to toggle. when the device is in the erase suspend-program mode, successive reads from the byte address of the non-erase suspend sector will indi- cate a logic 1 at the dq2 bit. note that a sector which is selected for erase is not available for read in erase suspend mode. other sectors which are not selected for erase can be read in erase suspend. dq6 is different from dq2 in that dq6 toggles only when the standard program or erase, or erase sus- pend-program operation is in progress. if the dq5 failure condition is observed while in sector erase mode (i.e., exceeded timing limits), the dq2 tog- gle bit can give extra information. in this case, the nor- mal function of dq2 is modified. if dq5 is at logic 1, then dq2 will toggle with consecutive reads only at the sector address that caused the failure condition. dq2 will toggle at the sector address where the failure oc- curred and will not toggle at other sector addresses. ry/by: ready/busy the am29f800 provides a ry/by open-drain output pin as a way to indicate to the host system that the em- bedded algorithms are either in progress or have been completed. if the output is low, the device is busy with either a program or erase operation. if the output is high, the device is ready to accept any read/write or erase operation. when the ry/by pin is low, the device will not accept any additional program or erase com- mands with the exception of the erase suspend com- mand. if the am29f800 is placed in an erase suspend mode, the ry/by output will be high. during programming, the ry/by pin is driven low after the rising edge of the fourth we pulse. during an erase operation, the ry/by pin is driven low after the rising edge of the sixth we pulse. the ry/by pin should be ignored while reset is at v il . refer to figure 13 for a detailed timing diagram. since this is an open-drain output, several ry/by pins can be tied together in parallel with a pull-up resis- tor to v cc . reset : hardware reset the am29f800 device may be reset by driving the reset pin to v il . the reset pin must be kept low (v il ) for at least 500 ns. any operation in progress will be terminated and the internal state machine will be reset to the read mode 20 m s after the reset pin is driven low. furthermore, once the reset pin goes high, the device requires an additional 50 ns before it will allow read access. when the reset pin is low, the device will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. if a hardware reset occurs during a program or erase operation, the data at that particular location will be indeterminate. the reset pin may be tied to the system reset input. therefore, if a system reset occurs during the embedded program or erase algorithm, the device
18 am29f800t/am29f800b 8/18/97 preliminary will be automatically reset to read mode and this will enable the systems microprocessor to read the boot-up firmware from the flash memory. byte/word configuration the byte pin selects the byte (8-bit) mode or word (16 bit) mode for the am29f800 device. when this pin is driven high, the device operates in the word (16 bit) mode. the data is read and programmed at dq0C dq15. when this pin is driven low, the device operates in byte (8 bit) mode. under this mode, the dq15/a-1 pin becomes the lowest address bit and dq8Cdq14 bits are tri-stated. however, the command bus cycle is always an 8-bit operation and hence commands are written at dq0Cdq7 and the dq8Cdq15 bits are ignored. refer to figures 15 and 16 for the timing diagram. data protection the am29f800 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power tran- sitions. during power up the device automatically re- sets the internal state machine in the read mode. also, with its control register architecture, alteration of the memory contents only occurs after successful comple- tion of specific multi-bus cycle command sequences. the device also incorporates several features to pre- vent inadvertent write cycles resulting from v cc power-up and power-down transitions or system noise. low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, the am29f800 locks out write cycles for v cc < v lko (see dc characteristics section for volt- ages). when v cc < v lko , the command register is disabled, all internal program/erase circuits are dis- abled, and the device resets to the read mode. the am29f800 ignores all writes until v cc > v lko . the user must ensure that the control pins are in the correct logic state when v cc > v lko to prevent unintentional writes. write pulse glitch protection noise pulses of less than 5 ns (typical) on oe , ce , or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write cycle ce and we must be a logical zero while oe is a logical one. power-up write inhibit power-up of the device with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to the read mode on power-up.
8/18/97 am29f800t/am29f800b 19 preliminary embedded algorithms figure 1. embedded programming algorithm start programming completed last address ? write program command sequence (see below) data poll device increment address ye s no 555h/aah 2aah/55h 555h/a0h program address/program data program command sequence (address/command): 20375c-6
20 am29f800t/am29f800b 8/18/97 preliminary embedded algorithms note: 1. to insure the command has been accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 were high on the second status check, the command may not have been ac- cepted. figure 2. embedded erase algorithm start erasure completed write erase command sequence (see below) data polling or toggle bit successfully completed 555h/aah 2aah/55h 555h/80h chip erase command sequence (address/command): 555h/aah 2aah/55h 555h/10h 555h/aah 2aah/55h 555h/80h individual sector/multiple sector erase command sequence (address/command): 555h/aah sector address/30h sector address/30h sector address/30h 2aah/55h additional sector erase commands are optional 20375c-7
8/18/97 am29f800t/am29f800b 21 preliminary figure 3. data polling algorithm start fail no dq7=data ? no pass ye s no ye s note: 1. dq7 is rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5. dq7=data ? dq5=1 ? yes read byte (dq0Cdq7) addr=va read byte (dq0Cdq7) addr=va va = byte address for programming = any of the sector addresses within the sector being erased during sector erase operation = valid address equals any non-protected sector group address during chip erase 20375c-8
22 am29f800t/am29f800b 8/18/97 preliminary figure 4. toggle bit algorithm figure 5. maximum negative overshoot waveform figure 6. maximum positive overshoot waveform start fail no dq6=toggle ? no pass yes no ye s note: 1. dq6 is rechecked even if dq5 = 1 because dq6 may stop toggling at the same time as dq5 changing to 1. dq6=toggle ? dq5=1 ? ye s read byte (dq0Cdq7) addr=dont care read byte (dq0Cdq7) addr=dont care 20375c-9 20 ns 20 ns +0.8 v C0.5 v 20 ns C2.0 v 20375c-10 20 ns v cc + 0.5 v 2.0 v 20 ns 20 ns v cc + 2.0 v 20375c-11
8/18/97 am29f800t/am29f800b 23 preliminary absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . C65 c to +125 c ambient temperature with power applied . . . . . . . . . . . . . C55 c to +125 c voltage with respect to ground all pins except a9 (note 1) . . . . . . . . C2.0 v to +7.0 v v cc (note 1). . . . . . . . . . . . . . . . . . . .C2.0 v to +7.0 v a9 (note 2). . . . . . . . . . . . . . . . . . . . C2.0 v to +13.0 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is C0.5 v. during voltage transitions, inputs may overshoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on input and i/o pins is v cc + 0.5 v. during voltage transitions, input and i/o pins may overshoot to v cc + 2.0 v for periods up to 20ns. 2. minimum dc input voltage on a9 pin is C0.5 v. during voltage transitions, a9 may overshoot v ss to C2.0 v for periods of up to 20 ns. maximum dc input voltage on a9 is +12.5 v which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output shorted to ground at a time. du- ration of the short circuit should not be greater than one second. stresses above those listed under absolute maximum rat- ings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. exposure of the device to absolute maximum rating conditions for ex- tended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature (t a ) . . . . . . . . . . .0 c to +70 c industrial (i) devices ambient temperature (t a ) . . . . . . . . .C40 c to +85 c extended (e) devices ambient temperature (t a ) . . . . . . . .C55 c to +125 c v cc supply voltages v cc for am29f800t/b-70, 90, 120, 150 . . . . . . . . . . . . . . . . . . . . +4.50 v to +5.50 v operating ranges define those limits between which the func- tionality of the device is guaranteed.
24 am29f800t/am29f800b 8/18/97 preliminary dc characteristics ttl/nmos compatible notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component (at 6 mhz). the frequency component typically is less than 2 ma/mhz, with oe at v ih . 2. i cc active while embedded program or erase algorithm is in progress. 3. not 100% tested. parameter symbol parameter description test conditions min max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 m a i lit a9 input load current v cc = v cc max, a9 = 13.0 v 35 m a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 m a i cc1 v cc active current (note 1) ce = v il , oe = v ih byte 40 ma word 50 i cc2 v cc active current (notes 2, 3) ce = v il , oe = v ih 60 ma i cc3 v cc standby current v cc = v cc max, ce = v ih , oe = v il 1.0 ma v il input low voltage C0.5 0.8 v v ih input high voltage 2.0 v cc + 0.5 v v id voltage for autoselect and temporary sector unprotect v cc = 5.25 volt 10.5 13.0 v v ol output low voltage i ol = 5.8 ma, v cc = v cc min 0.45 v v oh output high voltage i oh = C2.5 ma, v cc = v cc min 2.4 v v lko low v cc lock-out voltage 3.2 4.2 v
8/18/97 am29f800t/am29f800b 25 preliminary dc characteristics (continued) cmos compatible notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component (at 6 mhz). the frequency component typically is less than 2 ma/mhz, with oe at v ih . 2. i cc active while embedded program or erase algorithm is in progress. 3. not 100% tested. 4. i cc3 = 20 m a max at extended temperatures (>+85 c) parameter symbol parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 m a i lit a9 input load current v cc = v cc max, a9 = 13.0 v 35 m a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 m a i cc1 v cc active current (note 1) ce = v il , oe = v ih byte 20 40 ma word 28 50 i cc2 v cc active current (notes 2, 3) ce = v il , oe = v ih 30 50 ma i cc3 v cc standby current (note 4) v cc = v cc max, ce = v cc 0.3 v, oe = v il, reset = v cc 0.3 v 15 m a v il input low voltage C0.5 0.8 v v ih input high voltage 0.7 x v cc v cc + 0.3 v v id voltage for autoselect and temporary sector unprotect v cc = 5.25 volt 10.5 13.0 v v ol output low voltage i ol = 5.8 ma, v cc = v cc min 0.45 v v oh1 output low voltage i oh = C2.5 ma, v cc = v cc min 0.85 v cc v v oh2 i oh = C100 m a, v cc = v cc min v cc C0.4 v v lko low v cc lock-out voltage 3.2 4.2 v
26 am29f800t/am29f800b 8/18/97 preliminary ac characteristics read-only operations characteristics figure 7. test conditions parameter symbols description test setup speed options (notes 1 and 2) unit jedec standard -70 -90 -120 -150 t avav t rc read cycle time (note 4) min 70 90 120 150 ns t avqv t acc address to output delay ce = v il max 70 90 120 150 ns oe = v il t elqv t ce chip enable to output delay oe = v il max 70 90 120 150 ns t glqv t oe output enable to output delay max 30 35 50 55 ns t ehqz t df chip enable to output high z (notes 3, 4) max 20 20 30 35 ns t ghqz t df output enable to output high z (notes 3, 4) max 20 20 30 35 ns t axqx t oh output hold time from addresses, ce , or oe , whichever occurs first min0000ns t ready reset pin low to read mode (note 4) max 20 20 20 20 m s t elfl ce to byte switching low or high max 5 5 5 5 ns t elfh t flqz byte switching low to output high z (note 3) max 20 30 30 30 ns notes: 1. test conditions (for -70 only): output load: 1 ttl gate and 30 pf input rise and fall times: 5 ns input pulse levels: 0.0 v to 3.0 v timing measurement reference level input and output voltage: 1.5 v 2. test conditions (for all others): output load: 1 ttl gate and 100 pf input rise and fall times: 20 ns input pulse levels: 0.45 v to 2.4 v timing measurement reference level, input and output voltages: 0.8 v and 2.0 v 3. output driver disable time. 4. not 100% tested. 2.7 k w diodes = in3064 or equivalent c l 6.2 k w 5.0 v in3064 or equivalent notes: for -70: c l = 30 pf including jig capacitance for all others: c l = 100 pf including jig capacitance device under te s t 20375c-12
8/18/97 am29f800t/am29f800b 27 preliminary ac characteristics write/erase/program operations notes: 1. this does not include the preprogramming time. 2. not 100% tested. 3. these timings are for temporary sector unprotect operation. 4. output driver disable time. parameter symbols description -70 -90 -120 -150 unit jedec standard t avav t wc write cycle time (note 2) min 70 90 120 150 ns t avwl t as address setup time min 0 0 0 0 ns t wlax t ah address hold time min 45 45 50 50 ns t dvwh t ds data setup time min 30 45 50 50 ns t whdx t dh data hold time min 0 0 0 0 ns t oeh output enable hold time read (note 2) min 0 0 0 0 ns toggle and data polling (note 2) min 10 10 10 10 ns t ghwl t ghwl read recover time before write (oe high to we low) min 0 0 0 0 ns t elwl t cs ce setup time min 0 0 0 0 ns t wheh t ch ce hold time min 0 0 0 0 ns t wlwh t wp write pulse width min 35 45 50 50 ns t whwl t wph write pulse width high min 20 20 20 20 ns t whwh1 t whwh1 byte programming operation typ 7 7 7 7 m s t whwh2 t whwh2 sector erase operation (note 1) typ1111sec max 8 8 8 8 sec t vcs v cc set up time (note 2) min 50 50 50 50 m s t vidr rise time to v id min 500 500 500 500 ns t rp reset pulse width min 500 500 500 500 ns t busy program/erase valid to ry/by delay (note 2) min 30 35 50 55 ns t rsp reset setup time for temporary sector unprotect (notes 2, 3) min 4 4 4 4 m s
28 am29f800t/am29f800b 8/18/97 preliminary key to switching waveforms switching waveforms figure 8. ac waveforms for read operations must be steady may change from h to l may change from l to h does not apply dont care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state waveform inputs outputs ks000010 addresses ce oe we outputs addresses stable high z high z (t df ) (t oh ) output valid 20375c-13 t acc t oeh t oe (t ce ) t rc
8/18/97 am29f800t/am29f800b 29 preliminary switching waveforms notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. 6. these waveforms are for the x16 mode. figure 9. program operation timings notes: 1. sa is the sector address for sector erase. 2. these waveforms are for the x16 mode. figure 10. ac waveforms chip/sector erase operations d out pd t ah data polling t df t oh t oe t ds t cs t wph t dh t wp t ghwl addresses ce oe we data 5.0 v dq7 555h pa a0h pa 3rd bus cycle 20375c-14 t wc t rc t as t whwh1 t ce t as t wp t cs t dh 555h 2aah sa ce oe we data v cc aah 55h addresses 2aah t vcs t ds 555h 555h t wph t ghwl t ah aah 55h 80h 10h/30h 20375c-15 555 for chip erase
30 am29f800t/am29f800b 8/18/97 preliminary switching waveforms note: *dq7=valid data (the device has completed the embedded operation). figure 11. ac waveforms for data polling during embedded algorithm operations note: *dq6 stops toggling (the device has completed the embedded operation). figure 12. ac waveforms for toggle bit during embedded algorithm operations dq0Cdq6 valid data t oe dq7= valid data high z ce oe we dq7 dq7 dq0Cdq6 dq0Cdq6=invalid * 20375c-16 t oeh t ce t ch t df t oh t whwh 1 or 2 ce t oeh we oe dq6= stop toggling dq0Cdq7 valid dq6=toggle dq6=toggle data (dq0Cdq7) * t oe 20375c-17
8/18/97 am29f800t/am29f800b 31 preliminary switching waveforms figure 13. ry/by timing diagram during program/erase operations figure 14. reset timing diagram ce we ry/by t busy entire programming or erase operations the rising edge of the last we signal 20375c-18 reset 20375c-19 t ready t rp
32 am29f800t/am29f800b 8/18/97 preliminary switching waveforms figure 15. byte timing diagram for read operation figure 16. byte timing diagram for write operations ce oe byte t elfl t elfh dq0Cdq14 data output (dq0Cdq14) data output (dq0Cdq7) dq15/aC1 dq15 output address input 20375c-20 t flqz ce we byte the falling edge of the last we signal t hold (t ah ) t set (t as ) 20375c-21
8/18/97 am29f800t/am29f800b 33 preliminary notes: 1. all protected sectors unprotected. 2. all previously protected sectors are protected once again. figure 17. temporary sector unprotect algorithm figure 18. temporary sector unprotect timing diagram start perform erase or program operations reset = v ih temporary sector group unprotect completed (note 2) reset = v id (note 1) 20375c-22 0 v or 5 v 12 v program or erase command sequence reset ce we 0 v or 5 v t vidr t rsp 20375c-23
34 am29f800t/am29f800b 8/18/97 preliminary ac characteristics write/erase/program operations alternate ce controlled writes notes: 1. this does not include the preprogramming time. 2. not 100% tested. parameter symbols description -70 -90 -120 -150 unit jedec standard t avav t wc write cycle time (note 2) min 70 90 120 150 ns t avel t as address setup time min 0 0 0 0 ns t elax t ah address hold time min 45 45 50 50 ns t dveh t ds data setup time min 30 45 50 50 ns t ehdx t dh data hold time min 0 0 0 0 ns t oes output enable setup time min 0 0 0 0 ns t oeh output enable hold time read (note 2) min 0 0 0 0 ns toggle and data polling (note 2) min 10 10 10 10 ns t ghel t ghel read recover time before write min 0 0 0 0 ns t wlel t ws we setup time min 0 0 0 0 ns t ehwh t wh we hold time min 0 0 0 0 ns t eleh t cp ce pulse width min 35 45 50 50 ns t ehel t cph ce pulse width high min 20 20 20 20 ns t whwh1 t whwh1 byte programming operation typ 7 7 7 7 m s word programming operation typ 14 14 14 14 m s t whwh2 t whwh2 sector erase operation (note 1) typ1111sec max 8 8 8 8 sec t flqz byte switching low to output high z (note 2) max 20 30 30 30 ns
8/18/97 am29f800t/am29f800b 35 preliminary switching waveform notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. 6. these waveforms are for the x16 mode. figure 19. alternate ce controlled program operation timings d out p t ah data polling t ds t ws t cph t dh t cp t ghel addresses we oe ce data 5.0 volt dq7 555h pa a0h pa 20375c-24 t wc t as t whwh1
36 am29f800t/am29f800b 8/18/97 preliminary erase and programming performance notes: 1. the typical erase and programming times assume the following conditions: 25 c, 5.0 volt v cc , 100,000 cycles. these conditions do not apply to erase/program endurance. programming typicals assume checkerboard pattern. 2. the maximum erase and programming times assume the following conditions: 90 c, 4.5 volt v cc , 100,000 cycles. 3. although embedded algorithms allow for longer chip program and erase time, the actual time will be considerably less since bytes program or erase significantly faster than the worst case byte. 4. system-level overhead is defined as the time required to execute the four bus cycle command necessary to program each byte. in the preprogramming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. the embedded algorithms allow for 2.5 ms byte program time. dq5 = 1 only after a byte takes the theoretical maximum time to program. a minimal number of bytes may require significantly more programming pulses than the typical byte. the majority of the bytes will program within one or two pulses. this is demonstrated by the typical and maximum programming times listed above. latchup characteristics includes all pins except v cc . test conditions: v cc = 5.0 v, one pin at a time. parameter limits unit comments typ (note 1) max (note 2) sector erase time 1.0 8 sec excludes 00h programming prior to erasure chip erase time (note 3) 19 152 sec byte programming time (note 5) 7 300 m s excludes system-level overhead (note 4) word programming time (note 5) 14 600 m s chip programming time (notes 3, 5) 7.2 21.6 sec erase/program endurance 1,000,000 cycles minimum 100,000 cycles guaranteed min max input voltage with respect to v ss on all i/o pins C1.0 v v cc + 1.0 v v cc current C100 ma +100 ma
8/18/97 am29f800t/am29f800b 37 preliminary tsop pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25 c, f = 1.0 mhz. so pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25 c, f = 1.0 mhz. data retention parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 8 10 pf parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v pp = 0 8 10 pf parameter test conditions min unit minimum pattern data retention time 150 c10 years 125 c20 years
38 am29f800t/am29f800b 8/18/97 preliminary physical dimensions ts 048 48-pin standard thin small outline package (measured in millimeters) 48 25 1 24 18.30 18.50 19.80 20.20 11.90 12.10 0.05 0.15 0.50 bsc 0.95 1.05 16-038-ts48-2 ts 048 da101 8-8-94 ae pin 1 i.d. 1.20 max 0.50 0.70 0.10 0.21 0.25mm (0.0098") bsc 0 5 0.08 0.20
8/18/97 am29f800t/am29f800b 39 preliminary physical dimensions (continued) tsr048 48-pin reversed thin small outline package (measured in millimeters) 48 25 1 24 18.30 18.50 19.80 20.20 11.90 12.10 seating plane 0.05 0.15 0.50 bsc 0.95 1.05 16-038-ts48 tsr048 da104 8-8-94 ae pin 1 i.d. 1.20 max 0.50 0.70 0.10 0.21 0.25mm (0.0098") bsc 0 5 0.08 0.20
40 am29f800t/am29f800b 8/18/97 preliminary phyisical dimensions (continued) so 044 44-pin small outline package (measured in millimeters) 44 23 1 22 13.10 13.50 15.70 16.30 1.27 nom. 28.00 28.40 2.17 2.45 0.35 0.50 0.10 0.35 2.80 max. seating plane 16-038-so44-2 so 044 da82 11-9-95 lv 0.10 0.21 0.60 1.00 0 8 end view side view top view
8/18/97 am29f800t/am29f800b 41 preliminary revision summary for am29f800 distinctive characteristics: high performance: the fastest speed option available is now 70 ns. enhanced power management for standby mode: changed typical standby current to 1 m a. general description: added 70 ns speed option. product selector guide: added -70 column. pin configuration: added -70 speed option. ordering information, standard products: the -70 speed option is now listed in the example. valid combinations: added combinations for the -70 speed option. table 7, command definitions: corrected byte addresses for unlock and command cy- cles from 2aa to aaa. in the previous data sheet revision, the addresses for command definitions were shortened from four hexa- decimal digits to three. the more accurately represents the actual address bits required, a10Ca0. the remain- ing upper address bits are dont cares. the new address is compatible with the previous four- digit definition of aaaa; the only difference is that the highest-order hexadecimal digit a is now dont care. in fact, software programs written using the previous four-digit definitions do not require any changes; they remain completely compatible with the new three-digit definitions. the addresses for the byte-mode read cycles (fourth cycle) in the autoselect mode are corrected from 01h to 02h for device id, and from sax02h to sax04h for sector protect verification. note 5 is clarified. operating ranges: v cc supply voltages: added -70 speed option to the list. dc characteristics: cmos compatible: added column for typical i cc spec- ifications. revised max i cc specifications. ac characteristics: read only operations characteristics: added the -70 column and test conditions. test conditions, figure 7: changed speed option in first c l statement to -70. ac characteristics: write/erase/program operations, alternate ce con- trolled writes: added the -70 column; revised word/ byte programming and sector erase specifications. erase and programming performance: revised specifications. trademarks copyright ? 1997 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof, and expressflash are trademarks of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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